IEEE, IEEE Signal Processing Society, IEEE Circuits and Systems Society

L-Arch: DSP Architectures

Time: Wednesday, October 8, 10:15 - 12:15
Location: Commonwealth
Session Chair: Chaitali Chakrabarti, Arizona State University
 
L-Arch-1: A HIGHLY PARALLEL TURBO PRODUCT CODE DECODER WITHOUT INTERLEAVING RESOURCE
         Camille Leroux; Institut TELECOM, TELECOM Bretagne
         Christophe Jego; Institut TELECOM, TELECOM Bretagne
         Patrick Adde; Institut TELECOM, TELECOM Bretagne
         Michel Jezequel; Institut TELECOM, TELECOM Bretagne
         Deepak Gupta; Institut TELECOM, TELECOM Bretagne
 
L-Arch-2: A DIGIT-SERIAL ARCHITECTURE FOR INVERSION AND MULTIPLICATION IN GF(2M)
         Junfeng Fan; Katholieke Universiteit Leuven
         Ingrid Verbauwhede; Katholieke Universiteit Leuven
 
L-Arch-3: UNIFIED DECODER ARCHITECTURE FOR LDPC/TURBO CODES
         Yang Sun; Rice University
         Joseph Cavallaro; Rice University
 
L-Arch-4: EFFICIENT INTERPOLATION ARCHITECTURE FOR SOFT-DECISION REED-SOLOMON DECODING BY APPLYING SLOW-DOWN
         Xinmiao Zhang; Case Western Reserve University
         Jiangli Zhu; Case Western Reserve University
 
L-Arch-5: A 100MHZ REAL-TIME TONE MAPPING PROCESSOR WITH INTEGRATED PHOTOGRAPHIC AND GRADIENT COMPRESSION IN 0.13 UM TECHNOLGY
         Ching-Te Chiu; National Tsing Hua University
         Tsun-Hsien Wang; National Tsing Hua University
         Wei-Ming Ke; National Tsing Hua University
         Chen-Yu Chuang; National Tsing Hua University
         Jhih-Siao Huang; National Tsing Hua University
         Wei-Su Wong; National Tsing Hua University
         Ren-Song Tsay; National Tsing Hua University
 
L-Arch-6: A UNIFIED INSTRUCTION SET PROGRAMMABLE ARCHITECTURE FOR MULTI-STANDARD ADVANCED FORWARD ERROR CORRECTION
         Frederik Naessens; IMEC
         Bruno Bougard; IMEC
         Siebert Bressinck; IMEC
         Lieven Hollevoet; IMEC
         Praveen Raghavan; IMEC
         Liesbet Van der Perre; IMEC
         Francky Catthoor; IMEC